The invention is directed to a method for supplying a line with system clock signals which are formed either from clock signals over a first line exhibiting level fluctuations or are formed from digital clock pulses transmitted over a second line, in response to the level of the clock signals transmitted on the first line.
Methods are known in communications technology by which a clock is regenerated from a serial bit stream, this clock being utilized as a processing bit clock in communications-oriented equipment. In order to guarantee supplying the equipment with a bit clock in the absence of the in-coming bit stream, a switch is made to a bit clock generated internally in the equipment, using re-routing methods suitable for this purpose.
In the case of extremely high bit stream rates, for example such as in local or public ring networks, clock recovery methods based on surface wave filter technology are among those utilized. Such a clock regenerator equipped with surface wave filters, for data stream rates from 50 through 2OOM bits per second, is known from the Siemens publication, "LWL-Komponenten, Wandler, Senderund Empfaenger Messzubehoer", pages 92-93. The incoming data signals are first differentiated and rectified and supplied to a surface wave filter. Subsequently, the filtered output signal is again amplified and is available at an output as a regenerated clock. When, however, the incoming data bit stream comprises phase shifts, which frequently occur in ring networks because of the connection and disconnection of stations, then this leads to a significant lowering of the level of the clock signals present at the output and, when they fall below minimum voltage levels prescribed for defined circuit technologies, considerable disturbances result and undefined states in the system components can exist, for example, in the access controller of a ring network.